PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
7 CONTROL REGISTERS AND DATA STRUCTURES
7.1 General
The initial programming for the AAL1gator II is performed by loading the external memory with
specified information while a SW_RESET (refer to “SW_RESET” on page 165) is applied. The
SW_RESET state is entered after a hardware reset is removed, or it can be asserted by writing the
command register. After the memory is initialized, the CMD_REG_ATTN bit (refer to “CMD_
REG_ATTN” on page 166) should be set so the configuration data can be read. Then SW_
RESET can be removed. The device then reads the data structures from memory and enters the
correct operating mode.
Word data structures have the first byte located at the low-byte end of the bus, which is also the
location of the even data bytes (little endian implementation). Since there are 128K words of
memory and the memory itself is only 16 bits, complete byte pointers cannot be stored in 1-word
memory locations. To achieve 1-word pointers, all structures except the receive multiframe
buffers are stored in the first half of the memory. The receive buffers, which occupy 64K words,
are the only structures located in the second half of the memory.
Figure 83 on page 122 shows the distribution of the data structures within the AAL1gator II. All
registers except CMDREG are stored in the SRAM and all are readable.
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PMC [ PMC-SIERRA, INC ]
