PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
6.8 Miscellaneous Timing
6.8.1 SYS_CLK Timing
Figure 80 shows the timing for the SYS_CLK signal.
Ttol
Fc
Tp
Tdc
Tcl
Tch
SYS_CLK
Figure 80. SYS_CLK Timing
Signals
Symbol
Parameter
Min
Max
Unit
Fc
Tch
Tcl
Tp
SYS_CLK frequency
SYS_CLK high time
SYS_CLK low time
SYS_CLK period
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK*
40.00
MHz
ns
**
**
ns
25.7
**
ns
Tdc
Ttol
SYS_CLK duty cycle
SYS_CLK tolerance
**
50
%
ppm
NOTES: • The 8-line throughput is guaranteed only at Fc minimum of 38.87 MHz. For each line that is not used, the
minimum frequency can be decreased by 4.5 MHz, if SRTS is not used.
• *If TL_CLK synthesis is not used, this value can be relaxed to 200 ppm.
• ** The SYS_CLK pulse width and duty cycle is dependent on frequency, and external component selection.
Refer to section 8.6 “Board Requirements for the SRAM Interface” on page 174 for more detailed
requirements.
6.8.2 RESET Timing
Figure 81 shows the timing for the RESET signal.
Tres
/RESET(i)
Trec
/PROC_CS
Figure 81. Reset Timing
ꢀꢀꢈ
PMC [ PMC-SIERRA, INC ]
