PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
6.7 SRTS Timing
The SRTS interface timing requirements for the low-speed and high-speed interfaces are shown
respectively in Figure 78 and Figure 79. Low-speed SRTS timing is for UDF-ML, SDF-FR, and
SDF-MF modes; and high-speed SRTS timing is used for UDF-HS mode.
SYS_CLK
SRTS_STRB
Tq
ADAP_STRB
Tq
SRTS_LINE
Tq
SRTS_DOUT
Figure 78. Low-Speed SRTS Timing
Symbol
Parameter
Signals
Min
Max
Unit
Tq
Clock-to-output delay
SRTS_LINE, SRTS_DOUT,
SRTS_STRB, ADAP_SRTB
2
19
ns
N_CLK
Tq
SRTS_DOUT
SRTS_STRB
Tq
Thld
Tsu
Tq
Figure 79. High-Speed SRTS Timing
Symbol
Parameter
Signals
Min
Max
Unit
Tq
Clock-to-output delay
Data setup
SRTS_DOUT, SRTS_STRB
SRTS_DOUT
18
1
ns
Tsu
1
1
N_CLK
cycle
Thld
Data hold
SRTS_DOUT
1
N_CLK
cycle
ꢀꢀꢇ
PMC [ PMC-SIERRA, INC ]
