PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Symbol
Parameter
Signals
Min
Max
Unit
Taa
(Refer to
Acknowledge assertion after /CS
or /RD, whichever comes last
/PROC_ACK
5
29
SYS_CLK
periods
NOTE below)
Tasu17
Trd
Address setup time
Read operation time
MEM_ADDR
2
4
ns
4
SYS_CLK
periods
Tq
Clock-to-output delay
SP_DATA_CLK
2
2
15
15
ns
ns
Tded
Data enable delay from /MEM_
CS and /MEM_RD
/SP_DATA_EN, /MEM_CS,
/MEM_RD
Tdsu
Tdhld
Tcea
Data setup to SP_DATA_CLK
Data hold from SP_DATA_CLK
MEM_DATA
MEM_DATA
/PROC_ACK
15
15
2
ns
ns
ns
/PROC_CS deassertion to
/PROC_ACK deassertion
15
NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the
access begins, Taa will be a maximum of seven SYS_CLK periods. If the access
occurs immediately after another access, then Taa will be 23 to 29 SYS_CLK peri-
ods. Refer to section 6.5.3 “Microprocessor Holdoff Timing” for a description of
HOLDOFF activity.
6.5.3 Microprocessor Holdoff Timing
Figure 75 on page 116 shows the microprocessor holdoff timing. After the microprocessor
accesses the AAL1gator II, the holdoff circuit prevents the microprocessor from obtaining
another back-to-back access for 20 SYS_CLK cycles. However, holdoff does not apply while
SW_RESET, in the command register is set. The AAL1gator II holdoff counter is activated after
every processor access that occurs while the device is not in the RESET state. The holdoff counter
counts up to 20 and then freezes at that count. Microprocessor accesses are not honored unless
this count has completed.
/PROC_CS(i)
Thoff
HOLDOFF(o)
Figure 75. Microprocessor Holdoff Timing
ꢀꢀꢅ
PMC [ PMC-SIERRA, INC ]
