PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
bit is a logic 0, the TDLSIG data stream is inserted into Time Slot 16 and the
TDLCLK pin is a 50% duty cycle 64 kHz clock; otherwise, the TDLSIG data
stream is inserted into the Time Slot 0 National Use positions enabled by the
TXSAxEN bits.
In the default case TDLCLK is a bursted 4 kHz clock and TDLSIG is inserted
into the TS0 Sa4 bit.
RDLINTE:
The RDLINTE bit enables the RFDL received-data interrupt to also generate
an interrupt on the microprocessor interrupt, INTB.This allows a single
microprocessor to service the RFDL without needing to interface to the DMA
control signals. When RDLINTE is set to logic 1, an event causing an
interrupt in the RFDL (which is visible on the RDLINT output pin when
RXDMASIG is logic 1) also causes an interrupt to be generated on the INTB
output. When RDLINTE is set to logic 0, an interrupt event in the RFDL does
not cause an interrupt on INTB.
RDLEOME:
The RDLEOME bit enables the RFDL end-of-message interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
single microprocessor to service the RFDL without needing to interface to the
DMA control signals. When RDLEOME is set to logic 1, an end-of-message
event causing an EOM interrupt in the RFDL (which is visible on the
RDLEOM output pin when RXDMASIG is logic 1) also causes an interrupt to
be generated on the INTB output. When RDLEOME is set to logic 0, an EOM
interrupt event in the RFDL does not cause an interrupt on INTB. NOTE:
within the RFDL, an end-of-message event causes an interrupt on both the
EOM and INT RFDL interrupt outputs. See the Operation section for further
details on using the RFDL.
TDLINTE:
The TDLINTE bit enables the XFDL request for service interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
single microprocessor to service the XFDL without needing to interface to the
DMA control signals. When TDLINTE is set to logic 1, an request for service
interrupt event in the XFDL (which is visible on the TDLINT output pin when
TXDMASIG is logic 1) also causes and interrupt to be generated on the INTB
output. When TDLINTE is set to logic 0, an interrupt event in the XFDL does
not cause an interrupt on INTB.
TDLUDRE:
The TDLUDRE bit enables the XFDL transmit data underrun interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
73
PMC [ PMC-SIERRA, INC ]
