PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
SDN/RDN/RLCV, respectively. When RDPINV is set to logic 1, the interface
inverts the signal on the RDP/RDD input. When RDPINV is set to logic 0, the
interface passes the RDP/RDD signal unaltered. When RDNINV is set to logic
1, the interface inverts the signal on the RDN/RLCV input. When RDNINV is
set to logic 0, the interface passes the RDN/RLCV signal unaltered.
RUNI:
The RUNI bit enables the interface to receive unipolar digital data and line
code violation indications on the multifunction pins SDP/RDP/RDD and
SDN/RDN/RLCV. When RUNI is set to logic 1, the SDP/RDP/RDD and
SDN/RDN/RLCV multifunction pins become the data and line code violation
inputs, RDD and RLCV, sampled on the selected RCLKI edge. When RUNI is
set to logic 0, the SDP/RDP/RDD and SDN/RDN/RLCV multifunction pins
become the positive and negative pulse inputs, RDP and RDN, sampled on
the selected RCLKI edge.
RFALL:
The RFALL bit enables the Receive Interface to sample the multifunction pins
on the falling RCLKI edge. When RFALL is set to logic 1, the interface is
enabled to sample either the RDD and RLCV inputs, or the RDP and RDN
inputs, on the falling RCLKI edge. When RFALL is set to logic 0, the interface
is enabled to sample the inputs on the rising RCLKI edge.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
