PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 01H: E1XC Receive Backplane Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
0
0
0
0
0
X
R/W
R/W
R/W
R/W
R/W
RXDMAGAT
ROHM
BRX2RAIL
BRXSMFP
BRXCMFP
Unused
This register allows software to configure the Receive backplane interface format
of the E1XC.
RXDMAGAT:
The RXDMAGAT bit selects the gating of the RDLINT output with the
RDLEOM output when the internal HDLC receiver is used with DMA. When
RXDMAGAT is set to logic 1, the RDLINT DMA output is gated with the
RDLEOM output so that RDLINT is forced to logic 0 when RDLEOM is logic
1. When RXDMAGAT is set to logic 0, the RDLINT and RDLEOM outputs
operate independently.
BRX2RAIL:
The BRX2RAIL bit selects whether the backplane receive data signal on the
multifunction outputs BRPCM/BRDP and BRSIG/BRDN are in either dual rail
or single rail format. When BRX2RAIL is set to logic 1, the multifunction pins
become the BRDP and BRDN dual rail outputs, which contain the received
positive and negative line pulses timed to the 2.048MHz receive line rate,
RCLKO. When BRX2RAIL is set to logic 0, the multifunction pins become the
BRPCM and BRSIG digital outputs.
ROHM, BRXSMFP, BRXCMFP:
The ROHM, BRXSMFP and BRXCMFP bits select the output signal seen on
the backplane output BRFPO. The following table summarizes the
configurations:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PMC [ PMC-SIERRA, INC ]
