PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 02H: E1XC Datalink Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
RXDMASIG
Unused
0
X
0
X
0
0
0
0
R/W
TXDMASIG
Unused
R/W
R/W
R/W
R/W
RDLINTE
RDLEOME
TDLINTE
TDLUDRE
This register allows software to configure the datalink options of the E1XC.
RXDMASIG:
The RXDMASIG bit selects the internal HDLC receiver (RFDL) data-received
interrupt (INT) and end-of-message (EOM) signals to be output on the
RDLINT and RDLEOM pins. When RXDMASIG is set to logic 1, the RDLINT
and RDLEOM output pins can be used by a DMA controller to process the
datalink. When RXDMASIG is set to logic 0, the RFDL INT and EOM signals
are no longer available to a DMA controller; the signals on RDLINT and
RDLEOM become the extracted datalink data and clock, RDLSIG and
RDLCLK. In this mode, the data stream available on the RDLSIG output
corresponds to the extracted datalink from Time Slot 16 or the Time Slot 0
National Use bits depending on the state of the RXSAxEN bits of the Receive
TS0 Data Link Enables register.
TXDMASIG:
The TXDMASIG bit selects the internal HDLC transmitter (XFDL) request for
service interrupt (INT) and data underrun (UDR) signals to be output on the
TDLINT and TDLUDR pins. When TXDMASIG is set to logic 1, the TDLINT
and TDLUDR output pins can be used by a DMA controller to service the
datalink. When TXDMASIG is set to logic 0, the XFDL INT and UDR signals
are no longer available to a DMA controller; the signals on TDLINT and
TDLUDR become the serial datalink data input and clock, TDLSIG and
TDLCLK. In this mode an external controller is responsible for formatting the
data stream presented on the TDLSIG input to correspond to the datalink in
Time Slot 16 or the Time Slot 0 National Use bits. If the TRAN block
Configuration DLEN bit is logic 1 and the TRAN block Configuration SIGEN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PMC [ PMC-SIERRA, INC ]
