PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
the associated enable (RXSAxEN, x=4 to 8) set to logic 1. Depending on the
settings of the RXSAxEN bits, the effective bit rate of the data link may range
between 4 bit/s and 20 kbit/s. RDLSIG is generated on the falling edge of
RDLCLK.
Figure 17
- Receive Backplane Interface
BRCLK
BRFPI
BRFPO
BRPCM
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Undefined
Undefined
Undefined
A B C D
A B C D
A B C D
BRSIG
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 16
Timeslot 17
The Receive Backplane is configured to generate 2048 kbit/s, single-rail
formatted data with frame alignment indication.The Receive Backplane Options
register is programmed to BRX2RAIL=0, BRXSMFP=0 and BRXCMFP=0.
The BRFPI input pulse need not exist every frame; only one is required to align
the backplane signals. If no BRFPI pulse has been presented since reset, the
outputs will assume an arbitrary alignment.
If ROHM=0, BRXSMFP=0 and BRXCMFP=1, the BRFPO signal pulses high only
during the first bit of the first frame in the CRC multiframe.
If ROHM=0, BRXSMFP=1 and BRXCMFP=0, the BRFPO signal pulses high only
during the first bit of the frame containing the signalling multiframe alignment
signal.
If ROHM=0, BRXSMFP=1 and BRXCMFP=1, the BRFPO signal becomes high
on the falling BRCLK edge marking the beginning of bit 1 of frame 1 of every 16
frame signalling multiframe and returns low on the falling BRCLK edge marking
the end of bit 1 of frame 1 of every 16 frame CRC multiframe.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
193
PMC [ PMC-SIERRA, INC ]
