PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
the specific bit value is sourced from the TRAN block International/National
Control register. Depending on the settings of the TXSAxEN bits, the effective bit
rate of the data link may range between 4 bit/s and 20 kbit/s. TDLSIG is sampled
on the rising edge of TDLCLK.
Figure 15
-TS16 Receive Datalink Interface
Time Slots
15 16 171819 20 21 2223 2425 2627 28 2930 31
1 2 3 4 5 6 7 8 9 10 11 1213 1415 16
17
RPCM
0
RDLCLK
RDLSIG
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Data from time slot 16 extracted
and output serially over the
subsequent 32 time slots
When TS16 is selected as the source of the receive datalink (RXDMASIG=0 and
all of RXSAxEN=0), the 64 kbit/s TS16 data is presented on RDLSIG with an
accompanying RDLCLK with a period of 4 time slots. The data on RDLSIG is
generated on the falling edge of RDLCLK.
Figure 16
-TS0 Receive Datalink Interface
RCLKO
Timeslot 1
NFAS, Timeslot 0
FAS, Timeslot 1
7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5
7 8 1 2 3 4 5 6 7 8 1 2
RDPCM
7
8
4
5
6
Undefined
RDLSIG
RDLCLK
Undefined
When TS0 is selected as the source of the receive datalink (RXDMASIG=0 and
at least one RXSAxEN bit is a logic 1), the National Use bit of TS0 of the NFAS
frames data is presented on RDLSIG with an accompanying RDLCLK. A clock
pulse is generated on RDLCLK for each National Use bit on RDLSIG which has
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
192
PMC [ PMC-SIERRA, INC ]
