PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
11.1.1 Registers 49-4FH: Latching Performance Data
All the Performance Data registers are updated as a group by writing to any of
the PMON block count registers (addresses 49H-4FH). A write to any of these
locations loads performance data located in the PMON block into the internal
holding registers.The data contained in the holding registers can then be
subsequently read by µP accesses into the PMON block count register address
space.The latching of count data, and subsequent resetting of the counters, is
synchronized to the internal event timing so that no events are missed. NOTE: it
is necessary to write to one, and only one, count register address to latch all the
count data register values into the holding registers and to reset all the counters
for each polling cycle.
The PMON block is loaded with new performance data within 27 internal high-
speed clock periods of the latch performance data register write. With the XCLK
frequency at the nominal 16.384 MHz (or with the XCLK frequency at 49.152
MHz when using the jitter attenuator), the PMON registers should not be polled
until 1.7µsec have elapsed from the "latch performance data" register write.
When the E1XC is reset, the contents of the PMON count registers are unknown
until the first latching of performance data is performed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
175
PMC [ PMC-SIERRA, INC ]
