PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 48H: PMON Block Control/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTE
X
X
X
X
X
0
R/W
R
XFER
X
X
R
OVR
This register contains status information indicating when counter data has been
transferred into holding registers and indicating whether the holding registers
have been overrun.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the
transfer clock has caused the counter values to be stored in the PMON count
registers (49H - 4FH). A logic 1 in the INTE position enables the generation
of an interrupt; a logic 0 disables the generation of an interrupt. Note:The
INTE bit is not available if ID[6:0] = 0000000 binary in the E1XC
Revision/Chip ID register, indicating the E1XC rev. A.
XFER:
The XFER bit indicates that a transfer of counter data has occurred (and an
interrupt, if INTE is set to logic 1). A logic 1 in this bit position indicates that a
latch request, initiated by writing to one of the counter register locations, was
received and a transfer of the counter has occurred. A logic 0 indicates that
no transfer has occurred. The XFER bit and its interrupt are cleared
(acknowledged) by reading this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous interrupt has not been acknowledged before
the next transfer clock has been issued and that the contents of the holding
registers have been overwritten. A logic 0 indicates that no overrun has
occurred.The OVR bit is cleared by reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
174
PMC [ PMC-SIERRA, INC ]
