PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Reserved:
The reserved bit must be programmed to logic 0 to enable the correct output
format.
IND:
The IND bit controls the microprocessor access type: either indirect or direct.
The IND bit must be set to logic 1 for proper operation. When the E1XC is
reset, the IND bit is set low, disabling the indirect access mode.
PCCE:
The PCCE bit enables the per-timeslot functions. When the PCCE bit is set
to a logic 1, data inversion, trunk conditioning and signalling debouncing are
performed on a per-timeslot basis. When the PCCE bit is set to logic 0, the
per-timeslot functions are disabled.
Upon reset of the E1XC, the ACCEL, MTKC, IND, and PCCE bits are all set to
logic 0 disabling µP indirect access and per-timeslot functions.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
157
PMC [ PMC-SIERRA, INC ]
