PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 43H: SIGX BlockTime Slot Indirect Data Buffer
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
X
X
X
X
X
X
X
X
In the case of an indirect write, the Indirect Data Register holds the value that will
be written to the desired register when a write is initiated via the Timeslot Indirect
Address Register. In the case of an indirect read, the Indirect Data Register will
hold the contents of the indirectly addressed register, when the read has been
completed. Please refer below to the per-timeslot register descriptions for the
expected bit formats.
The signalling and per-timeslot functions are allocated within the registers as
follows:
Table 8
- SIGX Indirect Memory Map
21H
Signalling Data Register for Time Slot 1
22H
Signalling Data Register for Time Slot 2
•
•
•
•
•
•
2FH
Signalling Data Register for for Time Slot 15
31H
Signalling Data Register for Time Slot 17
•
•
•
•
•
•
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
160
PMC [ PMC-SIERRA, INC ]
