PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 40H: SIGX Block Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
ACCEL
Unused
Unused
Unused
MTKC
0
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
Reserved
IND
PCCE
This register allows selection of the microprocessor access type, and allows
enabling of the per-timeslot configuration registers.
ACCEL:
The ACCEL bit is used to enable an accelerated test mode for production
purposes only. For proper operation the ACCEL bit must be set to logic 0.
MTKC:
The master trunk conditioning bit, MTKC, enables trunk conditioning for all
timeslots, regardless of per-timeslot settings. A logic 1 in the MTKC bit
position enables master trunk conditioning data from all of the timeslot Trunk
Conditioning Data Registers (40H to 5FH) is output onto the data stream,
BRPCM and the per-timeslot signalling trunk conditioning bits A’,B’,C’ and D’
are output onto the signalling data stream, BRSIG. The MTKC bit is ORed
with the per-timeslot trunk conditioning enable bits in the Per-Timeslot
Configuration Registers to form the applied per-timeslot trunk conditioning
enables. When the E1XC is reset, the MTKC bit is set to logic 0, disabling
master trunk conditioning.
The MTKC bit is independent of the TRKEN bit of the E1XC Receive Options
register and takes precedence over it. If TRKEN is a logic 1, an out-of-frame
condition causes the the contents of the ELST Idle Code register to be placed
in all time slots on BRPCM. BRSIG presents the frozen signalling. If MTKC is
a logic 1, each BRPCM and BRSIG time slot may have an unique idle code.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
156
PMC [ PMC-SIERRA, INC ]
