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PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
Register 3AH: RFDL Block Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
R
R
R
R
R
FE  
X
X
X
X
X
X
X
X
OVR  
FLG  
EOM  
CRC  
NVB2  
NVB1  
NVB0  
NVB[2:0]:  
The NVB[2:0] bit positions indicate the number of valid bits in the RFDL  
Receive Data Register byte. It is possible that not all of the bits in the RFDL  
Receive Data Register are valid when the last data byte is read since the data  
frame can be any number of bits in length and not necessarily an integral  
number of bytes. The RFDL Receive Data Register is filled starting from the  
MSB bit position (RD7) and the data bits are shifted to lower bit positions as  
more bits are received, with one to eight data bits being valid. The number of  
valid bits is equal to 1 plus the value of NVB[2:0]. An NVB[2:0] value of 000  
binary indicates that only the FE bit in this register is valid. An NVB[2:0] value  
of 011 indicates that RD[7:4] contain valid data bits where RD4 is the data bit  
that was received first. NVB[2:0] is only valid when the EOM bit is a logic 1  
and the FLG bit is a logic 1 and the OVR bit is a logic 0.  
CRC:  
The CRC bit is set if a CRC error was detected in the last received LAPD  
frame. The CRC bit is only valid when EOM is logic 1 and FLG is a logic 1  
and OVR is a logic 0.  
On an interrupt generated from the detection of first flag, reading the Status  
register will return invalid NVB[2:0] and CRC bits, even though the EOM bit is  
logic 1 and the FLG bit is logic 1.  
EOM:  
The End of Message bit (EOM) follows the RDLEOM output. It is set when:  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
153  
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