PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 3BH: RFDL Block Receive Data
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
X
X
X
X
X
X
X
X
The RFDL Receive Data Register is filled starting from the MSB bit position
(RD7) and the data bits are shifted to lower bit positions as more bits are
received, with one to eight data bits being valid. The number of valid bits is equal
to 1 plus the value of NVB[2:0] from the RFDL Status Register. An NVB[2:0]
value of 111 indicates that RD[7:0] contain valid data bits where RD0
corresponds to the first bit of the serial byte received by the RFDL.
These registers are actually 4 level FIFOs. If data is available, the FE bit in the
Status register is low. If INTC[1:0] (in the RFDL Interrupt Control/Status register)
is set to 01, this register must be read within 31 data bit periods to prevent an
overrun. If INTC[1:0] is set to 11, this register must be read within 15 data bit
periods.
When an overrun is detected, an interrupt is generated and the FIFO is held
cleared until the Status register is read. When the LAPD abort sequence
(01111111) is detected in the data an ABORT interrupt is generated and the
data that has been shifted into the serial to parallel converter is written into the
FIFO.
A read of the Receive Data register increments the FIFO pointer at the end of the
read. If the Receive Data register read causes an FIFO underrun, then the
pointer is inhibited from incrementing. The underrun condition will be signalled in
the next Status read by returning all zeros.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
155
PMC [ PMC-SIERRA, INC ]
