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PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
1. The last byte in the LAPD frame (EOM) is being read from the Receive Data  
Register,  
2. An abort sequence is detected while not in the receiving all-ones state and  
the byte, written to the FIFO due to the detection of the abort sequence, is  
being read from the FIFO,  
3. The first flag has been detected and the dummy byte, written into the FIFO  
when the RFDL changes from the receiving all-ones state to the receiving  
flags state, is being read from the FIFO,  
4. Immediately on detection of FIFO overrun.  
The EOM bit is passed through the FIFO with the Data so that the Status will  
correspond to the Data just read from the FIFO.  
FLG:  
The flag bit (FLG) is set if the RFDL block has detected the presence of the  
LAPD flag sequence (01111110) in the data. FLG is reset only when the  
LAPD abort sequence (01111111) is detected in the data or when the RFDL  
block is disabled. This bit is passed through the FIFO with the Data so that  
the Status will correspond to the Data just read from the FIFO. The reception  
of bit-oriented codes over the data link will also force an abort due to its eight  
ones pattern.  
OVR:  
The Receiver Overrun bit (OVR) is set when data is written over unread data  
in the FIFO.This bit is not reset until after the Status register is read. While  
OVR is high, the RFDL and FIFO are held in the reset state, causing the FLG  
and EOM bits in the status register to be reset also.  
FE:  
The FIFO Empty bit (FE) is high when the last FIFO entry is read and goes  
low when the FIFO is loaded with new data.  
If the Receive Data register is read while there is no valid data, then a FIFO  
underrun condition occurs.The underrun condition is reflected in the Status  
register by forcing all bits to logic zero on the first Status register read  
immediately following the Received Data register read which caused the  
underrun condition.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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