PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 38H: RFDL Block Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
TR
X
X
X
X
X
X
0
R/W
R/W
EN
0
EN:
The enable bit (EN) controls the overall operation of the RFDL block. When
set, the RDFL block is enabled; when reset the RFDL block is disabled.
When the block is disabled, the FIFO and interrupts are all cleared, however,
the programming of the Enable/Status Register is not affected. When the
block is enabled, it will immediately begin looking for flags.
TR:
Setting the terminate reception bit (TR) forces the RFDL block to immediately
terminate the reception of the current LAPD frame, empty the FIFO, clear the
interrupts, and begin searching for a new flag sequence. The RFDL handles
the TR input in the same manner as if the EN bit had been cleared and then
set. The TR bit in the Configuration register will reset itself after a rising and
falling edge have occurred on the CLK input to the RFDL block once the write
to this register has completed and WRB goes inactive. If the Configuration
register is read after this time, the TR bit value returned will be zero.
The RFDL block handles the TR input in the same manner as clearing and
setting the EN bit, therefore, the RFDL state machine will begin searching for
flags and an interrupt will be generated when the first flag is detected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
150
PMC [ PMC-SIERRA, INC ]
