PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 13H: Alternate Loss of Signal Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
ALTLOSE
ALTLOSI
Unused
Unused
Unused
Unused
Unused
ALTLOS
0
X
X
X
X
X
X
X
R
The alternate loss of signal status provides a more stringent criteria for the
deassertion of the alarm.
ALTLOSE:
If the ALTLOSE bit is a logic 1, an interrupt is generated when the ALTLOS
status bit changes state.
ALTLOSI:
The LOSI bit is set high when the ALTLOS status bit changes state. It is
cleared when this register is read.
ALTLOS:
The ALTLOS bit is asserted when the number of consecutive zeros exceeds
the threshold specified by the CDRC Configuration register. The ALTLOS bit
is deasserted only after 255 bit periods during which no sequence of four
zeros has been received.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
107
PMC [ PMC-SIERRA, INC ]
