PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 11H: CDRC Block Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
LCVE
LOSE
0
0
HDB3E
Z4DE
0
0
Unused
Unused
Unused
Unused
X
X
X
X
The Interrupt Control Register is provided at CDRC read/write address 1.
The Z4DE, HDB3E, LOSE, and LCVE bits of this register are interrupt enable
bits used to select which of the indications (four consecutive zeros, HDB3
pattern, loss of signal, or line code violation) will generate an interrupt when their
status changes.
The occurrence of any of these events will generate an interrupt if there is a logic
1 in the corresponding bit position. When the E1XC is reset, Z4DE, HDB3E,
LOSE, and LCVE bits are set to logic 0, disabling any interrupt generation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
104
PMC [ PMC-SIERRA, INC ]
