PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Reserved:
The reserved bit must be cleared to logic 0 for correct operation.
ALGSEL:
The algorithm select (ALGSEL) bit determines the DPLL phase adjustment
algorithm. A logic 0 selects the original phase adjustment algorithm which
has 0.41 UIpp of high frequency jitter tolerance. When ALGSEL is logic 1, the
high frequency jitter tolerance is 0.50 UIpp, but the low frequency tolerance is
approximately 20% lower than the first algorithm.
O162:
If the AMI bit is logic 0, the ITU-T Recommendation O.162 compatibility select
bit (O162) allows selection between two line code definitions:
1. If O162 is a logic 0, a line code violation is indicated if the serial stream does
not match the verbatim HDB3 definition given in Recommendation G.703. A
bipolar violation that is not part of an HDB3 signature or a bipolar violation in
an HDB3 signature that is the same polarity as the last bipolar violation
results in a line code violation indication.
2. If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of
the same polarity as the last bipolar violation, as per ITU-T Recommendation
O.162.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
103
PMC [ PMC-SIERRA, INC ]
