PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 12H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
LCVI
LOSI
X
X
X
X
X
X
X
X
HDB3I
Z4DI
Unused
Unused
Unused
LOS
R
The LCVI, LOSI, HDB3I and Z4DI bits indicate which of the status events have
occurred since the last read of this register. A logic 1 indicates the
corresponding event was detected. These bits are cleared when the CDRC
Status Register is read.
LCVI:
The LCVI bit is asserted if a line code violation is detected. If the AMI bit of
the CDRC Configuration Register is a logic 1, LCVI becomes a logic 1 if two
consecutive marks are of the same polarity (i.e. on the same pin, RDP or
RDN). If the AMI and O162 bits of the CDRC Configuration Register is a logic
0, LCVI becomes a logic 1 if a bipolar violation (BPV) is of the same polarity
as the previous BPV or if the BPV is not preceded by two spaces. If the AMI
bit is a logic 0 and the O162 bit is a logic 1, LCVI becomes a logic 1 if two
consecutive bipolar violations are of the same polarity.
LOSI:
The LOSI bit is set high when the LOS status bit changes state.
HDB3I:
The HDB3I bit is set high if an HDB3 signature, which is a bipolar violation of
the opposite polarity of the previous bipolar violation following two spaces, is
detected in the received data stream.
Z4DI:
The Z4DI bit is set high if four consecutive spaces occur.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
105
PMC [ PMC-SIERRA, INC ]
