PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0038H: STLI Clock Configuration
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
Reserved
Unused
0
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
TDCLKOEN
0
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
TDCLKOEN:
The transmit clock enable (TDCLKOEN) bit controls the gating of the internal parallel transmit
clock. When TDCLKOEN is set to logic 1, the TDCLKO output clock operates normally.
When TDCLKOEN is set to logic 0, the TDCLKO output clock is held low. This register bit
should be set to loic 1 for normal operation.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
134
PMC [ PMC-SIERRA, INC ]
