PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
The programmable transmit clock frequency selection (PGMTCLKSEL) bit selects the
frequency of the PGMTCLK output clock. When PGMTCLKSEL is set high, PGMTCLK is a
nominal 8 KHz clock. When PGMTCLKSEL is set to logic zero, PGMTCLK is a nominal
Register 0040H: RRMP Configuration
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R
BUSY
Unused
X
Unused
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
LREIBLK
Reserved
Reserved
LBIPEACCBLK
Reserved
SBIPEACCBLK
Reserved
Reserved
Reserved
LRDI3
0
0
0
0
0
0
1
0
1
0
0
0
X
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LAIS3
Bit 1
ALGO2
Bit 0
FOOF
FOOF:
The force out of frame (FOOF) bit forces out of frame condition. When a logic 1 is written to
FOOF, the framer block is forced out of frame at the next frame boundary regardless of the
framing pattern value. The OOF event initiates re framing in an upstream frame detector.
ALGO2:
The ALGO2 bit selects the framing pattern used to determine and maintain the frame
alignment. When ALGO2 is set to logic 1, the framing pattern consist of the 8 bits of the first
A1 framing bytes and the first 4 bits of the last A2 framing bytes (12 bits total). This algorithm
examines only 12 framing bits; all other framing bits are ignored. When ALGO2 is set to logic
0, the framing patterns consist of 12 A1 framing bytes and 12 A2 framing bytes.
LAIS3:
The line alarm indication signal detection (LAIS3) bit selects the Line AIS detection algorithm.
When LAIS3 is set to logic 1, Line AIS is declared when a 111 pattern is detected in bits 6,7,8
of the K2 byte for three consecutive frames. When LAIS3 is set to logic 0, Line AIS is
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
136
PMC [ PMC-SIERRA, INC ]
