S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
10.16.1Phase Comparison
The phase comparison between the receive recovered clock (RCLK) and the transmit reference
clock (REFCLK+/-) is implemented by sampling, at a fixed interval specified by the Reference
Counter, the output of the Phase Counter. The Reference Counter is clocked by RCLK while
the Phase Counter is clocked by the REFCLK+/- clock.
Successive reading of the value obtained, referred to as the phase sample (PHSAMP), can be
used to calculate the phase relation between both clocks. Both the Reference Counter and the
Phase Counter are programmable counters and are set to have equal cycle period. Therefore, if
REFCLK+/- was phased locked to RCLK, successive readings of the phase sample would be
equal. The phase sample value will increase or decrease depending if REFCLK+/- is faster or
slower than RCLK.
At each reference period, a signal enabling the sampling (SAMPLEN) of the Phase Counter is
produced. This signal is resynchronized to REFCLK+/- to avoid any potential metastability
problem that could result due to the asynchronous nature of both clocks.
10.16.2Phase Reacquisition Control
The Phase Reacquisition Control circuit prevents using the phase sample from both sides of the
counter wrap-around point when performing the Phase Sample averaging. The Phase Count is
first divided in four quadrants, each equal to approximately a quarter of the Phase Count.
Comparators are used to determine in which quadrant each phase sample is located. When two
successive samples (one in the first quadrant and the other in the last quadrant) are seen, the
Reference Phase Alignment Flag (RPHALFLG) is generated.
Upon reception of this signal, the Phase Counter is reset to align the phase count sampling point
towards its middle count. This signal is also sent to the Phase Averager circuit. The generation
of this signal may be squelched by setting the AUTOREAC bit of the WANS configuration
register.
10.16.3Phase Averager
To provide some noise immunity and improve the resolution of the phase detector algorithm of
the WANS, the phase samples are averaged over a programmable number of samples.
Although referred to as an averaging process, it is truly an accumulation process. It retains full
resolution, i.e. no division is performed on the accumulated value. The Phase Word includes an
integer and a fractional part. The number of averaging samples sets the size of the fractional
part.
A programmable counter, the Sample Counter, is incremented at each SAMPLEN signal. This
Sample Counter defines the Phase Averaging Period, equal to the Reference Period times the
programmed number of phase samples. At the end of this period, the accumulated phase sample
value is transferred to the Phase Word register. The Phase Word (PHAWORD) is then
accessible by an external processor. A timer flag (TIMFLG) is raised at the end of each
averaging period. The flag may be used to generate an interrupt request to an external
processor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
90
PMC [ PMC-SIERRA, INC ]
