S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
In general, the management functions include filling the receive FIFO, indicating when the
receive FIFO contains packet data or cells, maintaining the receive FIFO read and write
pointers, and detecting FIFO overrun conditions.
The interface accepts a read clock (RFCLK) and read enable signal (RENB) when data is read
from the receive FIFO (using the rising edge of the RFCLK). The start of packet RSOP marks
the first byte of receive packet data on the RDAT[31:0]. The RPRTY signal determine the
parity on the RDAT[31:0] bus (selectable as odd or even parity). The end of a packet is
indicated by the REOP signal with the RMOD[1:0] signals indicating the number of valid bytes
on RDAT[31:0]. Signal RERR is provided to indicate that an error in the received packet has
occurred (the error may have several causes include an abort sequence or a FCS error).
The RVAL signal is used to indicate when RSOP, REOP, RERR, RMOD[1:0] and RDAT[31:0]
are valid. This interface also indicates FIFO overruns via a maskable interrupt and register bits.
Read accesses while RVAL is low are ignored and will output invalid data. RVAL will not
assert until RENB is asserted.
10.17.3Transmit UTOPIA Level 3 Interface
The Transmit UTOPIA/POS-PHY Level 3 Interface (TUL3) provides FIFO management and
the S/UNI-8x155 transmit cell interface. Each channel receive FIFO may contain up to four
cells. The FIFO depth may be programmed from 4 to 1 cells. The FIFO provides the cell rate
decoupling function between the transmission system physical layer and the ATM layer.
In general, the management functions include emptying cells from the transmit FIFO, indicating
when the transmit FIFO is full, maintaining the transmit FIFO read and write pointers and
detecting a FIFO overrun condition.
The UTOPIA Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal
(TENB), the start of a cell (TSOC) indication and the parity bit (TPRTY) when data is written to
the transmit. The TADR[2:0] bus with TCA is used to poll the channel FIFOs for fill status. As
well, channels are selected using the TADR[2:0] and falling edge of TENB. To reduce FIFO
latency, the FIFO depth at which TCA indicates “full” can be set to one, two, three or four cells
by the FIFODP[1:0] bits of the TUL3. If the programmed depth is less than 16, more than one
cell may be written after TCA is asserted as the TUL3 still allows 16 cells to be stored in its
FIFO.
The interface also indicates FIFO overruns via a maskable interrupt and register bits. The
TXCP automatically transmits idle cells until a full cell is available to be transmitted.
10.17.4Transmit POS-PHY Level 3 Interface
The Transmit UTOPIA/POS-PHY Level 3 Interface (TUL3) provides FIFO management at the
S/UNI-8x155 transmit packet interface. Each channel transmit FIFO contains 256 bytes. The
FIFO provides the system rate decoupling function between the transmission system physical
layer and the link layer, and to handle timing differences caused by the insertion of escape
characters.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
92
PMC [ PMC-SIERRA, INC ]
