S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Because it indicates that the averaging process includes invalid sample values, the RPHALFLG
signal also prevents the Phase Word register from being updated at the end of the current Phase
Averaging period. The RPHAFLG signal indicates this event by sending the Reference Phase
Alignment condition signal (RPHALGN) to the Microprocessor interface status register. The
RPHALGN signal is reset at the end of the following valid Phase Averaging period.
10.17 ATM UTOPIA and Packet over SONET/SDH POS-PHY System
Interfaces
The S/UNI-8x155 system interface can be configured for UTOPIA or POS-PHY modes of
operation.
When configured for UTOPIA operation, the S/UNI-8x155 implements a multi-PHY UTOPIA
Level 3 interface to allow the transfer of ATM cells between the ATM layer device and the
S/UNI-8x155.
When configured for POS-PHY operation, the S/UNI-8x155 implements a multi-PHY POS-
PHY Level 3 interface. In this mode, the S/UNI-8x155 supports POS applications or
applications requiring a mix of channels provisioned for POS and ATM operation. In this mixed
operation, ATM cells are transferred as fixed-length packets over the POS-PHY Level 3
interface.
10.17.1Receive UTOPIA Level 3 Interface
The Receive UTOPIA/POS-PHY Level 3 Interface (RUL3) provides FIFO management at the
S/UNI-8x155 receive cell interface during UTOPIA Level 3 operation. Each channel receive
FIFO may contain up to four cells. The FIFO provides the cell rate decoupling function
between the transmission system physical layer and the ATM layer.
In general, the management functions include filling the receive FIFO, indicating when the
receive FIFO contains cells, maintaining the receive FIFO read and write pointers, and detecting
FIFO overrun conditions.
The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal
(RENB). The RADR[2:0] bus with RCA is used to poll the channel FIFOs for fill status. As
well, channels are selected using the RADR[2:0] and falling edge of RENB. The interface
indicates the start of a cell (RSOC) when data is read on the receive RDAT[31:0] bus. The
RPRTY signal reports the parity on the RDAT[31:0] bus (selectable as odd or even parity). This
interface also indicates FIFO overruns via a maskable interrupt and register bits.
10.17.2Receive POS-PHY Level 3 Interface
The Receive UTOPIA/POS-PHY Level 3 Interface (RUL3) provides FIFO management at the
S/UNI-8x155 receive interface during POS-PHY Level 3 operation. Each channel receive FIFO
contains 256 bytes. The FIFO provides the system rate decoupling function between the
transmission system physical layer and the link layer, and to handle timing differences caused
by the removal of escape characters.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
91
PMC [ PMC-SIERRA, INC ]
