S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
10.4 The Receive APS, Synchronization Extractor and Bit Error
Monitor (RASE)
10.4.1 Automatic Protection Switch Control
The Automatic Protection Switch (APS) control block filters and captures the receive automatic
protection switch channel bytes (K1 and K2) allowing them to be read via the RASE APS K1
Register and the RASE APS K2 Register. The bytes are filtered for three frames before being
written to these registers. A protection switching byte failure alarm is declared when twelve
successive frames have been received, where no three consecutive frames contain identical K1
bytes. The protection switching byte failure alarm is removed upon detection of three
consecutive frames containing identical K1 bytes. The detection of invalid APS codes is done
in software by polling the RASE APS K1 Register and the RASE APS K2 Register.
10.4.2 Bit Error Rate Monitor
The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error detection code
(B2) based on the line overhead and synchronous payload envelope of the receive data stream.
The line BIP-24 code is a bit interleaved parity calculation using even parity. Details are
provided in the references. The calculated BIP code is compared with the BIP-24 code
extracted from the B2 bytes of the following frame. Any differences indicate that a line layer
bit error has occurred. Up to 192,000 (24 BIP/frame x 8000 frames/second) bit errors can be
detected per second for STS-3c/STM-1 rate.
The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read
via the microprocessor interface. During a read, the counter value is latched and the counter is
reset to 0 (or 1, if there is an outstanding event). Note: This counter should be polled at least
once per second to avoid saturation that in turn may result in missed bit error events.
The BERM block is able to simultaneously monitor for signal fail (SF) or signal degrade (SD)
threshold crossing and provide alarms through software interrupts. The bit error rates
-3
-9
associated with the SF or SD alarms are programmable over a range of 10 to 10 . Details are
provided in the Operations section.
10.4.3 Synchronization Status Extraction
The Synchronization Status Extraction (SSE) Block extracts the synchronization status (S1)
byte from the line overhead. The SSE block can be configured to capture the S1 nibble after
three or after eight frames with the same value (filtering turned on) or after any change in the
value (filtering turned off). The S1 nibble can be read via the Microprocessor Interface.
10.5 Receive Path Overhead Processor (RPOP)
The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of
path overhead, extraction of the synchronous payload envelope, and path level alarm indication
and performance monitoring.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
71
PMC [ PMC-SIERRA, INC ]
