S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
10.3.2 Line AIS Detect
The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS) in the
receive stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of
the K2 byte, for three or five consecutive frames. Line AIS is removed when any pattern other
than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The
LAIS signal is optionally reported on the RALRM output pin when enabled by the LAISEN
Receive Alarm Control Register bit.
10.3.3 Data Link Extract Block
The Data Link Extract Block extracts the line data communication channel (bytes D4 to D12)
from the STS-3c/STM-1 stream. The extracted bytes are serialized and output on the associated
RDCC output at a nominal 576 kbit/s rate. Timing for downstream processing of the data
communication channel is provided by the RDCLK output. RDCLK is derived from a 2.16
MHz clock that is gapped to yield an average frequency of 576 kHz.
10.3.4 Error Monitor Block
The Error Monitor Block calculates the received line BIP-8 error detection codes based on the
Line Overhead bytes and synchronous payload envelopes of the STS-3c/STM-1 stream. The
line BIP-8 code is a bit interleaved parity calculation using even parity. Details are provided in
the references. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from
the following frame. Any differences indicate that a line layer bit error has occurred. Optionally
the RLOP can be configured to count a maximum of only one BIP error per frame.
This block also extracts the line FEBE code from the M1 byte. The FEBE code is contained in
bits 2 to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in
the last frame by the far end. The FEBE code value has 25 legal values (0 to 24) for an STS-
3c/STM-1 stream. Illegal values are interpreted as zero errors.
The Error Monitor Block accumulates B2 error events and FEBE events in two 20-bit saturating
counters that can be read via the Microprocessor Interface. The contents of these counters may
be transferred to internal holding registers by writing to any one of the counter addresses, or by
using the TIP register bit feature. During a transfer, the counter value is latched and the counter
is reset to 0 (or 1, if there is an outstanding event). Note: These counters should be polled at
least once per second to avoid saturation.
The B2 error event counters optionally can be configured to accumulate only "word" errors. A
B2 word error is defined as the occurrence of one or more B2 bit error events during a frame.
The B2 error counter is incremented by one for each frame in which a B2 word error occurs.
In addition the FEBE events counters optionally can be configured to accumulate only "word"
events. A FEBE word event is defined as the occurrence of one or more FEBE bit events during
a frame. The FEBE event counter is incremented by one for each frame in which a FEBE event
occurs. If the extracted FEBE value is in the range 1 to 4 the FEBE event counter will be
incremented for each and every FEBE bit. If the extracted FEBE value is greater than 4 the
FEBE event counter will be incremented by 4.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
70
PMC [ PMC-SIERRA, INC ]
