S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin
No.
Function
RVAL
The POS-PHY receive data valid (RVAL) signal indicates
when the POS-PHY bus is valid during POS-PHY.
When RVAL is high and RENB is low, the values on
RDAT[31:0], RPRTY, RSOP, REOP, RERR and RMOD[1:0]
are valid. When RVAL is low, the values on RDAT[31:0],
RPRTY, RSOP, REOP, RERR and RMOD[1:0] are invalid
and must be ignored.
The value on RVAL is updated on the next clock rising edge
when RENB is sampled low. RVAL is updated on the rising
edge of RFCLK.
9.7 Microprocessor Interface Signals
Pin Name
Type
Pin
Function
No.
CSB
Input
C24
The active-low chip select (CSB) signal is low during S/UNI-
8x155 register accesses.
When CSB is high, the RDB and WRB inputs are ignored.
When CSB is low, the RDB and WRB are valid. CSB must
be high when RSTB is low to properly reset the chip.
If CSB is not required (i.e., registers accesses are controlled
using the RDB and WRB signals only), CSB must be
connected to an inverted version of the RSTB input.
RDB
Input
Input
I/O
B24
E23
The active-low read enable (RDB) signal is low during S/UNI-
8x155 register read accesses. The S/UNI-8x155 drives the
D[7:0] bus with the contents of the addressed register while
RDB and CSB are low.
The active-low write strobe (WRB) signal is low during a
S/UNI-8x155 register write accesses. The D[7:0] bus
contents are clocked into the addressed register on the rising
WRB edge while CSB is low.
WRB
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D23
C23
B23
A23
E22
D22
C22
B22
The bi-directional data bus D[7:0] is used during S/UNI-
8x155 register read and write accesses.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
Input
B28
C27
B27
A27
E26
D26
C26
B26
D25
C25
B25
A25
E24
The address bus A[12:0] selects specific registers during
S/UNI-8x155 register accesses.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
56
PMC [ PMC-SIERRA, INC ]
