S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin
No.
Function
RMOD[0]
RMOD[1]
Output
AD29
The POS-PHY receive modulo (RMOD) indicates the number
of valid bytes of data on RDAT[31:0] during POS-PHY
operation.
AD30
The value on the RMOD[1:0] bus when REOP is high
specifies the number of valid bytes of packet data on
RDAT[31:0]. RMOD is set to “00” when REOP is low.
RMOD[1:0] = "00"RDAT[31:0] valid
RMOD[1:0] = "01"RDAT[31:8] valid
RMOD[1:0] = "10"RDAT[31:16] valid
RMOD[1:0] = "11"RDAT[31:24] valid
The value on RMOD[1:0] is updated on the next clock rising
edge when RENB is sampled low. RMOD[1:0] is only used
for POS-PHY operation and is updated on the rising edge of
RFCLK.
RSX
Output
AD31
The POS-PHY receive start of transfer (RSX) indicates when
the in-band port address is present on the RDAT[31:0] bus
during POS-PHY Level 3 operation.
When RSX is high, the value on RDAT[7:0] is the address of
the receive PHY channel being selected. Subsequent data
transfers on the RDAT[31:0] bus will read the channel FIFO
buffer specified by this in-band address.
The value on RSX is updated on the next clock rising edge
when RENB is sampled low. RSX is only used for POS-PHY
operation and is updated on the rising edge of RFCLK.
RADR[0]
RADR[1]
RADR[2]
Input
AE27
AE28
AE29
The UTOPIA receive port address select (RADR[2:0]) is used
to select the channel whose FIFO fill status is to be polled or
the channel for which a UTOPIA cell transfer is desired.
When RENB transitions from high to low, the value sampled
on RADR[2:0] selects the channel FIFO which the ATM cell
is read from. During all other conditions, the fill status of the
channel FIFO with the address sampled on RADR[2:0] is
reported on RCA.
RADR[2:0] is sampled on the rising edge of RFCLK.
RCA
Output
AD28
The UTOPIA receive cell available (RCA) is used to
determine the fill status of each channel FIFO during
UTOPIA operation.
RCA is used to poll the channel FIFOs to determine the
number of ATM cells that are in the FIFO. The address
sampled on RADR[2:0] will cause RCA to be updated with
the channel information on the following clock cycle.
When RCA is set high, the channel FIFO has at least one
complete ATM cell. When RCA is set low, the channel FIFO
does not contain a complete ATM cell.
RCA is updated on the rising edge of RFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
55
PMC [ PMC-SIERRA, INC ]
