S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
9.6 Receive ATM (UTOPIA) and Packet over SONET/SDH (POS)
System Interface
Pin Name
Type
Pin
Function
No.
RFCLK
Input
AF30
The UTOPIA receive FIFO read clock (RFCLK) is used to
read ATM cells from the cell receive FIFO.
In UTOPIA operation, RFCLK must cycle at a 104 MHz to
60 MHz instantaneous rate, and must be a free running clock
(cannot be gapped).
The POS-PHY receive FIFO read clock (RFCLK) is used to
read packet data from the packet FIFO.
In POS-PHY operation, RFCLK must cycle at a 104 MHz to
60 MHz instantaneous rate, and must be a free running clock
(cannot be gapped).
Note:
Running this interface below 90MHz might result in limited
device performance with respect to throughput for all
possible packet sizes for both UTOPIA and POS-PHY modes
of operation.
RPRTY
Output
AC30
The UTOPIA receive parity (RPRTY) signal indicates the
parity of the RDAT[31:0] bus. Odd or even parity may be
selected using software control.
In UTOPIA operation, the value on RPRTY is updated on the
following clock cycle when RENB is sampled low.
RPRTY is updated on the rising edge of RFCLK.
The POS-PHY receive parity (RPRTY) indicates the parity of
the RDAT[31:0] bus. Odd or even parity may be selected
using software control.
In POS-PHY operation, the value on RPRTY is updated on
the next clock cycle when RENB is sampled low.
RPRTY is updated on the rising edge of RFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
52
PMC [ PMC-SIERRA, INC ]
