S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0C1, 0x1C1, 0x2C1, 0x3C1, 0x4C1, 0x5C1, 0x6C1, 0x7C1:
TXFP Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
XOFF
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
1
0
Reserved
FCSERR
FCSSEL[1]
FCSSEL[0]
Reserved
DSCR
FIFORST
FIFORST:
The FIFORST bit is used to reset the 256-byte transmit channel buffer. When FIFORST is
set to logic zero, the channel buffer operates normally. When FIFORST is set to logic one,
the buffer is emptied of all octets (including the current packet being transmitted) and
ignores writes. The buffer remains empty and continues to ignore writes until a logic zero is
written to FIFORST. Flags are transmitted until a subsequent packet is written to the FIFO.
The FIFORST must be set high before the per-channel FIFO reset in the TUL3 is asserted.
The FIFORST must be set low after the per-channel FIFO reset in the TUL3 is deasserted.
DSCR:
The DSCR bit controls the scrambling of the POS frames. When DSCR is a logic one,
scrambling is enabled. When DSCR is a logic zero, payload scrambling is disabled.
FCSSEL[1:0]:
The Frame Control Sequence select (FCSSEL[1:0]) bits allow to control the FCS
calculation according to the table below. The FCS is calculated over the whole packet data,
before byte stuffing and scrambling.
FCSSEL[1:0]
FCS Operation
No FCS inserted
CRC-16.ISO-3309 (2 bytes)
CRC-32 (4 bytes)
Reserved
00
01
10
11
FCSERR:
The FCSERR bit controls the insertion of FCS errors for diagnostic purposes. When
FCSERR is set to logic one, if FCS insertion is enabled, the FCS octets are inverted prior to
insertion in the POS frame. When FCSERR is set low, the FCS is inserted normally.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
264
PMC [ PMC-SIERRA, INC ]
