S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0B1, 0x1B1, 0x2B1, 0x3B1, 0x4B1, 0x5B1, 0x6B1, 0x7B1:
RXFP Receive FCS Error Frame Count LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
RFCSEF[7]
RFCSEF[6]
RFCSEF[5]
RFCSEF[4]
RFCSEF[3]
RFCSEF[2]
RFCSEF[1]
RFCSEF[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 0x0B2, 0x1B2, 0x2B2, 0x3B2, 0x4B2, 0x5B2, 0x6B2, 0x7B2:
RXFP Receive FCS Error Frame Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFCSEF[15]
RFCSEF[14]
RFCSEF[13]
RFCSEF[12]
RFCSEF[11]
RFCSEF[10]
RFCSEF[9]
RFCSEF[8]
X
X
X
X
X
X
X
X
RFCSEF[15:0]:
The RFCSEF[15:0] bits indicate the number of POS frames received with an FCS error
during the last accumulation interval. A write to any one of the RXFP Receive FCS Error
Frame Counter registers loads the registers with the current counter value and resets the
internal counter to zero.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
260
PMC [ PMC-SIERRA, INC ]
