S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0B5, 0x1B5, 0x2B5, 0x3B5, 0x4B5, 0x5B5, 0x6B5, 0x7B5:
RXFP Receive Maximum Length Error Frame Counter LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
RMAXLF[7]
RMAXLF[6]
RMAXLF[5]
RMAXLF[4]
RMAXLF[3]
RMAXLF[2]
RMAXLF[1]
RMAXLF[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 0x0B6, 0x1B6, 0x2B6, 0x3B6, 0x4B6, 0x5B6, 0x6B6, 0x7B6:
RXFP Receive Maximum Length Error Frame Counter MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RMAXLF[15]
RMAXLF[14]
RMAXLF[13]
RMAXLF[12]
RMAXLF[11]
RMAXLF[10]
RMAXLF[9]
RMAXLF[8]
X
X
X
X
X
X
X
X
RMAXLF[15:0]:
The RMAXLF[15:0] bits indicate the number of POS frames exceeding the maximum
packet length that were received during the last accumulation interval. A write to any one
of the RXFP Receive Maximum Length Error Frame Counter registers loads the registers
with the current counter value and resets the internal counter to zero.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
262
PMC [ PMC-SIERRA, INC ]
