S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x088, 0x188, 0x288, 0x388, 0x488, 0x588, 0x688, 0x788:
TXCP Transmit Cell Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
TCELL[23]
TCELL[22]
TCELL[21]
TCELL[20]
TCELL[19]
TCELL[18]
TCELL[17]
TCELL[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
TCELL[23:0]:
The TCELL[23:0] bits indicate the number of cells read from the transmit FIFO and
inserted into the transmission stream during the last accumulation interval. Idle cells
inserted into the transmission stream are not counted. A write to any one of the TXCP
Transmit Cell Counter registers loads the registers with the current counter value and resets
the internal count to zero.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
242
PMC [ PMC-SIERRA, INC ]
