S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x05C, 0x15C, 0x25C, 0x35C, 0x45C, 0x55C, 0x65C, 0x75C:
CRSI Configuration
Bit
Type
R/W
R/W
R/W
R/W
Function
SDINV
Reserved
SENB
Reserved
Unused
LOTI
Default
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
X
R
R
R
ROOLI
DOOLI
DOOLI:
The DOOLI bit is the data out of lock interrupt status bit. DOOLI is set high when the the
DOOLV bit changes state, indicating that either the CRU has locked to the incoming data
stream or has gone out of lock. DOOLI is cleared when this register is read.
ROOLI:
The ROOLI bit is the reference out of lock interrupt status bit. ROOLI is set high when the
ROOLV register changes state, indicating that either the PLL is locked to the reference
clock REFCLK or in out of lock. ROOLI is cleared when this register is read.
LOTI:
The LOTI bit is the loss of transition interrupt status bit. LOTI is set high when a loss of
transition event occurs. A loss of transition is defined as either the SD input set low or more
than 96 consecutive ones or zeros received. LOTI is cleared when this register is read.
Reserved:
All reserved bits must be programmed to default values for proper operation.
SENB:
The loss of signal transition detector enable (SENB) bit enables the declaration of loss of
transition (LOT) when more than 96 consecutive ones or zeros occurs in the receive data.
When SENB is a logic zero, a loss of transition is declared when more than 96 consecutive
ones or zeros occurs in the receive data or when the SD input is low. When SENB is a logic
one, a loss of transition is declared only when the SD input is low.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
215