S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x004, 0x104, 0x204, 0x304, 0x404, 0x504, 0x604, 0x704:
Channel Master Configuration #1
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Function
TPTBEN
TSTBEN
SDH_J0/Z0
TFPEN
DLE
PDLE
Reserved
CHTIP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
X
CHTIP:
The CHTIP bit is set to a logic one when the channel’s performance monitor registers are
being loaded. Writing to the channel’s Interrupt Status #2 register (0x007, 0x107, 0x207 or
0x307) initiates an accumulation interval transfer and loads all the performance monitor
registers in the channel’s RSOP, RLOP, RPOP, SSTB, SPTB, RXCP, TXCP, RXFP and
TXFP blocks.
Writing to the S/UNI-8x155 Master Reset and Identity register (0x000) will cause all
channels to load their performance monitor registers. This operation is equivalent to writing
to each channel’s Interrupt Status #2 register (0x007, 0x107, 0x207 or 0x307).
CHTIP remains high while the transfer is in progress, and is set to a logic zero when the
transfer is complete. CHTIP can be polled by a microprocessor to determine when the
accumulation interval transfer is complete.
Reserved:
Reserved bit must be programmed to zero for proper operation.
PDLE:
The Parallel Diagnostic Loopback, PDLE bit enables the channel’s diagnostic loopback
where the channel’s Transmit Section Overhead Processor (TSOP) is directly connected to
its Receive Section Overhead Processor (RSOP). When PDLE is logic one, loopback is
enabled. Under this operating condition, the channel continues to operates normally in the
transmit direction. When PDLE is logic zero, the channel operates normally in both
directions.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
118
PMC [ PMC-SIERRA, INC ]
