STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
LREFCLK
Input W12
Line Reference Clock (LREFCLK). This signal
provides reference timing for the SONET telecom bus
interface. On the incoming byte interface of the
telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL,
LDTPL, LDV5, LDAIS and LAC1 are sampled of the
rising edge or LREFCLK. In the outgoing byte
interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 and
LAOE are updated on the rising edge of LREFCLK.
This clock is nominally a 19.44MHz +/-20ppm clock
with a 50% duty cycle. This clock can be external
connected to SREFCLK. When in Transparent VT
mode this clock must be connected to SREFCLK.
LAC1
Input W13
Line Add C1 Frame Pulse (LAC1). The Add bus
timing signal identifies the frame and multiframe
boundaries on the Add Data bus LADATA[7:0].
LAC1 is set high to mark the first C1 byte of the first
transport envelope frame of the 4 frame multiframe on
the LADATA[7:0] bus. LAC1 need not be presented on
every occurrence of the multiframe .
LAC1 is sampled on the rising edge of LREFCLK.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
38
PMC [ PMC-SIERRA, INC ]
