STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
ECLK[1]
I/O
AB3
Y4
Egress Clock (ECLK[1:28]). When the Clock Master
Clear Channel mode is active, ECLK[x] is an output
and is used to sample the associated egress data,
ED[x]. ECLK[x] is a version of the transmit clock[x]
which is generated from the receive clock or the
common transmit clock, CTCLK.
ECLK[2]
ECLK[3]
Y19
AA21
AB22
V22
T21
T22
AB1
T1
ECLK[4]
ECLK[5]
ECLK[6]
ECLK[7]
When in Clock Slave: Clear Channel mode ECLK[x] is
ECLK[8]
an input and is used to sampled ED[x].
ECLK[9]
ED[x] is sampled on the active edge of the associated
ECLK[x].
ECLK[10]
ECLK[11]
ECLK[12]
ECLK[13]
ECLK[14]
ECLK[15]
ECLK[16]
ECLK[17]
ECLK[18]
ECLK[19]
ECLK[20]
ECLK[21]
ECLK[22]
ECLK[23]
ECLK[24]
ECLK[25]
ECLK[26]
ECLK[27]
ECLK[28]
G2
G3
ECLK[1] shares a pin with the DS3 system interface
U21
V19
D21
C21
U4
output signal TFPO/TMFPO/TGAPCLK.
R1
D3
F1
T20
U22
B22
D20
L3
K4
E4
F2
Recovered T1 and E1 Clocks
RECVCLK1
Output D22
Recovered Clock 1 (RECVCLK1). This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
RECVCLK2
Output C22
Recovered Clock 2 (RECVCLK2). This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
Telecom Line Side Interface
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
37
PMC [ PMC-SIERRA, INC ]
