STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
T1 and E1 System Side Serial Clock and Data Interface
ICLK[1]
Output Y3
Ingress Clocks (ICLK[1:28]). The Ingress Clocks are
active when the external signaling interface is disabled.
Each ingress clock is optionally a smoothed (jitter
attenuated) version of the associated receive clock
from either the SONET/SDH mapper or the DS3
multiplexer. When the Clock Master: NxChannel mode
is active, ICLK[x] is a gapped version of the smoothed
receive clock. When Clock Master: Full T1/E1 mode is
active, IFP[x] and ID[x] are updated on the active edge
of ICLK[x]. When the Clock Master: NxDS0 mode is
active, ID[x] is updated on the active edge of ICLK[x].
ICLK[2]
AB2
ICLK[3]
AB20
AB21
W22
Y20
H22
F19
W3
AA1
H3
ICLK[4]
ICLK[5]
ICLK[6]
ICLK[7]
ICLK[8]
ICLK[9]
ICLK[10]
ICLK[11]
ICLK[12]
ICLK[13]
ICLK[14]
ICLK[15]
ICLK[16]
ICLK[17]
ICLK[18]
ICLK[19]
ICLK[20]
ICLK[21]
ICLK[22]
ICLK[23]
ICLK[24]
ICLK[25]
ICLK[26]
ICLK[27]
ICLK[28]
H1
L22
K19
F22
G20
T3
In E1 mode only ICLK[1:21] is used.
ICLK[1] shares a pin with the DS3 system interface
signal RGAPCLK/RSCLK.
U1
D1
C1
H19
G19
E19
F21
K3
J4
E3
D2
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
33
PMC [ PMC-SIERRA, INC ]
