PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
DJAT exhibits negligible jitter gain for jitter frequencies below 6.6 Hz, and
attenuates jitter at frequencies above 6.6 Hz by 20 dB per decade. In most
applications the DJAT Block will determine jitter attenuation for higher jitter
frequencies only. Wander, below 10 Hz for example, will essentially be passed
unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated
as specified, however, outgoing jitter may be dominated by the generated
residual jitter in cases where incoming jitter is insignificant. This generated
residual jitter is directly related to the use of 24X (37.056 MHz) digital phase
locked loop for transmit clock generation. The block allows the implied jitter
attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and
the implied jitter attenuation requirements for a type II customer interface given in
ANSI T1.403 to be met.
8.23.2 JitterTolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a
device can accept without exceeding its linear operating range, or corrupting
data. For DJAT, the input jitter tolerance is 29 Unit Intervals peak-to-peak (UIpp)
with a worst case frequency offset of 354 Hz. It is 48 UIpp with no frequency
offset. The frequency offset is the difference between the frequency of XCLK
divided by 24 and that of the input data clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
51
PMC [ PMC-SIERRA, INC ]
