PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Data to be transmitted is provided on an interrupt-driven basis by writing to a
double-buffered transmit data register. Upon completion of the frames, a CRC-
CCITT frame check sequence is transmitted, followed by idle flag sequences. If
the transmit data register underflows, an abort sequence is automatically
transmitted.
When enabled for use (via the EN bit in the XFDL Configuration register), the
XFDL continuously transmits the flag character (01111110). Data bytes to be
transmitted are written into the Transmit Data Register. After the parallel-to-serial
conversion of each data byte, an interrupt is generated to signal the controller to
write the next byte into the Transmit Data Register. After the last data frame byte
is transmitted, the CRC word (if CRC insertion has been enabled), or a flag (if
CRC insertion has not been enabled) is transmitted.The XFDL then returns to
the transmission of flag characters.
If there are more than five consecutive ones in the raw transmit data or in the
CRC data, a zero is stuffed into the serial data output.This prevents the
unintentional transmission of flag or abort characters.
Abort characters can be continuously transmitted at any time by setting a control
bit. During transmission, an underrun situation can occur if data is not written to
the Transmit Data Register before the previous byte has been depleted. In this
case, an abort sequence is transmitted, and the controlling processor is notified
via the TDLUDR signal. Optionally, the interrupt and underrun signals can be
independently enabled to also generate an interrupt on the INTB output,
providing a means to notify the controlling processor of changes in the XFDL
operating status.
When the internal HDLC transmitter is disabled, the serial data to be transmitted
on the Facility Data Link can be input on the TDLSIG pin timed to the clock rate
output on the TDLCLK pin.
8.22 Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse
density enforcement is enabled by a register bit within the XPDE.
This block monitors the digital output of the transmitter, detecting when the
stream is about to violate the ANSI T1.403 12.5% pulse density rule over a
moving 192-bit window. If a density violation is detected, the TSB can be
enabled to insert a logic 1 into the digital stream to ensure the resultant output
no longer violates the pulse density requirement. When the XPDE is disabled
from inserting logic 1s, the digital stream from the transmitter is passed through
unaltered.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
49
PMC [ PMC-SIERRA, INC ]
