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PM4341A-QI 参数 Datasheet PDF下载

PM4341A-QI图片预览
型号: PM4341A-QI
PDF下载: 下载PDF文件 查看货源
内容描述: T1成帧器/收发器 [T1 FRAMER/TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路
文件页数/大小: 288 页 / 981 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM4341AT1XC  
DATA SHEET  
PMC-900602  
ISSUE 7  
T1 FRAMER/TRANSCEIVER  
8.23.4 Frequency Range  
In the non-attenuating mode, that is, when the FIFO is within one UI of  
overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The  
guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200  
Hz with worst case jitter (29 UIpp) and maximum XCLK frequency offset (± 100  
ppm). The nominal range is 1.544 MHz ± 963 Hz with no jitter or XCLK  
frequency offset.  
8.24 Timing Options (TOPS)  
The Timing Options block provides a means of selecting the source of the  
internal input clock to the DJAT TSB, the reference signal for the digital PLL, and  
the clock source used to derive the output TCLKO signal.  
8.25 Digital DS-1Transmit Interface (DTIF)  
The Digital DS-1 Transmit Interface provides control over the various output  
options available on the multifunctional digital transmit pins TDP/TDD and  
TDN/TFLG. When configured for dual-rail output, the multifunctional pins  
become the TDP and TDN outputs. These outputs can be formatted as either  
return-to-zero (RZ) or non-return-to-zero (NRZ) signals and can be updated on  
either the rising or falling edge of TCLKO. When the interface is configured for  
single-rail output, the multifunctional pins become the TDD and TFLG outputs,  
which can be enabled to be updated on either the rising or falling TCLKO edge.  
Further, the TFLG output can be enabled to indicate FIFO empty or FIFO full  
status.  
The DTIF block also provides Alarm Indication Signalling (AIS) generation  
capability by generating alternating mark signals on the TDP/TDN outputs, or all-  
ones on the TDD output, when the TAISEN bit is set in the Transmit DS1 Interface  
Configuration register.This is useful when the internal loopback modes are used.  
8.26 Analog DSX-1 Pulse Generator (XPLS)  
The Analog DSX-1 Pulse Generator function is provided by the XPLS block.This  
block converts Non Return to Zero (NRZ) pulses into Alternate Mark Inversion  
(AMI) line signals suitable for use in the DSX-1 intra-office environment. The  
dual-rail NRZ pulses are supplied by the DJAT block. A logical "1" on the TDP  
output from DJAT causes a positive pulse to be transmitted; a similar signal on  
the TDN output from DJAT causes a negative pulse to be transmitted. If both  
TDP and TDN are logical "0" or "1," no output pulse is transmitted.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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