PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Figure 8
- DJAT JitterTolerance
100
29
28
10
DJAT minimum
tolerance
Jitter
acceptable
Amplitude,
UIpp
1.0
unacceptable
0.2
0.1
0.01
1
10
4.9
100 0.3k
Jitter Frequency, Hz
1k
10k
100k
The accuracy of the XCLK frequency and that of the DJAT PLL reference input
clock used to generate the jitter-free TCLKO have an effect on the minimum jitter
tolerance. Given that the DJAT PLL reference clock accuracy can be ±200 Hz
from 1.544 MHz, and that the XCLK input accuracy can be ±100 ppm from
37.056 MHz, the minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK/24 are shown in Figure 9.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
52
PMC [ PMC-SIERRA, INC ]
