PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
when the data byte written into the RFDL FIFO buffer due to the
transition from receiving all ones to flags is read.
•
RDLEOM is set low by reading the RFDL Status Register or by disabling the
RFDL.
8. The TDLUDR output goes high when the processor is unable to service the
TDLINT request for more data within a specific time-out period. This period is
dependent upon the frequency of TDLCLK:
for a TDLCLK frequency of 4 kHz (ESF FDL at the full 4 kHz rate),
the time-out is 1.0 ms;
•
•
•
for a TDLCLK frequency of 2 kHz (half the ESF FDL), the time-out
is 2.0ms;
for a TDLCLK frequency of 8 kHz (T1DM R-bit insertion), the time-
out is 500µs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
35
PMC [ PMC-SIERRA, INC ]
