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PM4341A-QI 参数 Datasheet PDF下载

PM4341A-QI图片预览
型号: PM4341A-QI
PDF下载: 下载PDF文件 查看货源
内容描述: T1成帧器/收发器 [T1 FRAMER/TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路
文件页数/大小: 288 页 / 981 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM4341AT1XC  
DATA SHEET  
PMC-900602  
ISSUE 7  
T1 FRAMER/TRANSCEIVER  
3. Inputs RSTB and ALE have integral pull-up resistors.  
4. Pins 1,19,20,21,39,40,41,59,60,61,79, and 80 on the 80-pin PQFP are not  
connected. These pins should be left unconnected in any application.  
5. The TDLSIG/TDLINT pin has an integral pull-up resistor and defaults to being  
an input after a reset.  
6. When the internal RFDL is enabled, the RDLINT output goes high:  
when the number of bytes specified in the RFDL Interrupt  
Status/Control Register have been received on the data link,  
immediately on detection of RFDL FIFO buffer overrun,  
immediately on detection of end of message,  
immediately on detection of an abort condition, or,  
immediately on detection of the transition from receiving all ones to  
flags.  
The interrupt is cleared at the start of the next RFDL Data Register read that  
results in an empty FIFO buffer. This is independent of the FIFO buffer fill  
level for which the interrupt is programmed. If there is still data remaining in  
the buffer, RDLINT will remain high. An interrupt due to a RFDL FIFO buffer  
overrun condition is not cleared on a RFDL Data Register read but on a  
RFDL Status Register read. The RDLINT output can always be forced low by  
disabling the RFDL (setting the EN bit in the RFDL Configuration Register to  
logic 0, or by disabling the internal HDLC receiver in the T1XC Receive Data  
Link Configuration Register), or by forcing the RFDL to terminate reception  
(setting the TR bit in the RFDL Configuration Register to logic 1).  
The RDLINT output may be forced low by disabling the interrupts with the  
RFDL Interrupt Status/Control Register. However, the internal interrupt latch  
is not cleared, and the state of this latch can still be read through the RFDL  
Interrupt Status/Control Register.  
7. The RDLEOM output goes high:  
immediately on detection of RFDL FIFO buffer overrun,  
when the data byte written into the RFDL FIFO buffer due to an end  
of message condition is read,  
when the data byte written into the RFDL FIFO buffer due to an  
abort condition is read, or,  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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