PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Pin
Pin No.
Name
Type
PQFP PLCC Function
WRB
Input
18
30
3
26
35
11
Active low write strobe (WRB).This signal
is pulsed low to enable a T1XC register
write access. The D[7:0] bus contents
are clocked into the addressed normal
mode register on the rising edge of WRB
+ CSB, where ‘+’ indicates a logical or.
ALE
Input
Address latch enable (ALE).This signal
latches the address bus contents, A[7:0],
when low, allowing the T1XC to be
interfaced to a multiplexed address/data
bus. When ALE is high, the address
latches are transparent.
RSTB
Input
Input
Active low reset (RSTB). This signal is set
low to asynchronously reset the T1XC.
RSTB is a Schmitt-trigger input with
integral pull-up.
A[0]
22
23
24
25
26
27
28
29
27
28
29
30
31
32
33
34
68
20
44
61
Address bus (A[7:0]).This bus selects
specific registers during T1XC register
accesses.
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
VDDO[0]
VDDO[1]
VDDO[2]
VDDO[3]
Power 69
Pad ring power pins (VDDO[3:0]).These
pins must be connected to a common,
well decoupled +5 VDC supply together
with the VDDI[1:0] pins. Care must be
taken to avoid coupling noise induced on
the VDDO pins into the VDDI pins.
12
42
62
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
32
PMC [ PMC-SIERRA, INC ]
