PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
PMC-Sierra has verified the operation of the RSLC functional block with the
following transformers:
• Pulse Engineering PE64931 (1:1:1) and PE64952 (1:2CT)
• BH Electronics 500-1775 (1:1:1) and 500-1777 (1:2CT)
Many manufacturers produce dual transformers containing the 1:2 CT and 1:1.36
transformers necessary for the receiver and transmitter circuits. PMC-Sierra has
verified the operation of XPLS and RSLC with the following dual parts:
• Pulse Engineering PE64952
• Pulse Engineering PE65774 (for extended temperature range)
BH Electronics 500-1777
8.3 Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is provided by a Data and Clock
Recovery (CDRC) block.The CDRC provides clock and PCM data recovery,
B8ZS decoding, line code violation detection, and loss of signal detection. It
recovers the clock from the incoming RZ data pulses using a digital phase-
locked-loop and recovers the NRZ data. Loss of signal is indicated after 176
consecutive bit periods of the absence of pulses on both the positive and
negative line pulse inputs and is cleared after the occurrence of a single line
pulse. If enabled, a microprocessor interrupt is generated when a loss of signal
is detected and when the signal returns. A line code violation is defined as a
bipolar violation (BPV) for AMI-coded signals and is defined as a BPV that is not
part of a zero substitution code for B8ZS-coded signals.
The input jitter tolerance of CDRC complies with the Bell Core Document
TA-TSY-000170 and with the AT&T specification TR62411.The tolerance is
measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC
block provides two algorithms for clock recovery that result in differing jitter
tolerance characteristics.The first algorithm (when the ALGSEL register bit is
logic 0) provides good low frequency jitter tolerance, but the high frequency
tolerance is close to the TR62411 limit.The second algorithm (when ALGSEL is
logic 1) provides much better high frequency jitter tolerance (approaching
0.5UIpp) at the expense of the low frequency tolerance; the low frequency
tolerance of the second algorithm is approximately 80% of that of the first
algorithm.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
39
PMC [ PMC-SIERRA, INC ]
